IBM System 360 Model 30 VHDL files
This update: 2010-07-16
This page contains the VHDL source for a 360/30 implementation, plus compiled files suitable for use on a Digilent Spartan 3 board.
The VHDL is a literal translation of the diagrams that can be found in the FMD manual (Bitsavers mirror). Where errors are suspected, these are flagged in the VHDL, typically using "??".
The Model 30 was implemented using transparent latches and SR flip-flops. These are not a good fit for an FPGA, which prefers edge-triggered flip-flops, but as the timing requirements are not onerous it works well. There are some cases where explicit delays have been added to allow the circuitry to work as intended.
The front panel output is via VGA using the 3-bit interface provided on the board. Switch inputs are via multiplexed rotary switches, and the on-board pushbuttons and slide switches. Both the panel and switch sections are in their own files for ease of modification. The switch file contains details of how the switches are wired in. Basically, the 10 hex-encoded switches are scanned via 10 outputs and 4 inputs, and the remaining 8 switch inputs are discrete. The 'PROC' positions are not connected, so disconnecting the entire switch assembly defaults all switches to the 'Process' position.
If anyone ports this to an alternative FPGA board, please let me have the relevant files and I will host them here.
- Manuals you will need (these are mirrored from BitSavers)
- 360/30 Functional Characteristics GA24-3231-7_360-30_funcChar
- 360/30 Maintenance Diagram Manual (MDM) R25-5103-1_2030CPUsch_Aug65
- 360/30 Field Engineering Theory of Operations Manual (FETOM) Y24-3360-1_2030_FE_Theory_Opns_Jun67
- 360/30 Operating Guide A24-3373-2_Model_30_Operating_Guide_Dec66
- 360/30 Field Engineering (FE) Handbook 229-2116-2_360_30_FE_Handbook
- Compiled image for Spartan3: ibm2030.bit and Platform Flash: 2030.mcs
- A zip file containing all the files below: ljw2030.zip
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Support files
- README Information about this project
- COPYING GPL Licence Information
- Gates2030 Basic gate and flipflop definitions
- Buses2030 System-wide definitions for buses etc.
- digilentSP3.ucf Constraints file for Spartan 3 Starter Kit
- ccros20100715 Microcode image
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ibm2030 Top level
- ibm2030-vga Virtual front panel
- switches Switch handling
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cpu Main CPU
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FMD2030_UDC1 CCROS, WX, registers
- FMD2030_5-01A-B ROS ind & chk, ROSAR backup & assm
- FMD2030_5-01C-D SALS & CTRL reg, ROS 1-4k
- FMD2030_5-02A-B X6,X7 generation, W-X reg gating
- FMD2030_5-03A Priority controls
- FMD2030_5-03B Stg wrap
- FMD2030_5-03C Clock start & stop ctrls
- FMD2030_5-03D Manual controls
- FMD2030_5-04A-B Recycle controls & Address match
- FMD2030_5-04C Manual data, C,F,H regs
- FMD2030_5-04D R/W Stg Controls
- FMD2030_5-05A R reg ind & chks, 1401 stats
- FMD2030_5-05B M-N assem
- FMD2030_5-05C Regs & A,B assm
- FMD2030_5-05D R/W stg clock 1st 32k
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FMD2030_UDC2 ALU,Memory, Multiplexor channel
- FMD2030_5-06A-B A,B,Z Ind, Chks, Immed Stats, A,B regs, ALU
- FMD2030_5-06C-D R reg assm & stg to mem
- FMD2030_5-07A1 MN ind
- FMD2030_5-07A2 Check reg
- FMD2030_5-07B1 SAR
- FMD2030_5-07B2 S reg
- FMD2030_5-07C Direct Control
- FMD2030_5-08A1 CPU clock
- FMD2030_5-08A2 Mpx ind
- FMD2030_5-08B Q reg & Stg protect
- FMD2030_5-08C Mpx FO & FB
- FMD2030_5-08D Mpx FA
- FMD2030_UDC3 1050, Selector channels - still to come
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FMD2030_UDC1 CCROS, WX, registers
